Intel® Purley Platform

The new Intel® Purley Platform, with new 14nm microarchitecture codename: Skylake

Advanced Features Are Designed into the Silicon

Synergy among compute, network, and storage is built in. Intel® Xeon® Scalable processors optimize interconnectivity with a focus on speed without compromising data security. Here are just a few of the value-added features:

Pervasive, Breakthrough Performance

The new microarchitecture provides increased per-core and socket-level performance.

Accelerate Compute-Intensive Workloads

Intel® AVX-512 can accelerate performance for workloads such as video and image analytics, cryptography, and signal processing.

Integrated Intel® Ethernet with iWARP RDMA

Speeds of up to 4x10GbE with iWARP RDMA provides low-latency, high-throughput data communication integrated in the chipset.

Integrated Intel® QuickAssist Technology (Intel® QAT)

Data compression and cryptography acceleration, frees the host processor, and enhances data transport and protection across server, storage, network, and VM migration. Integrated in the chipset.

Integrated Intel® Omni-Path Architecture (Intel® OPA)

End-to-end high-bandwidth, low-latency fabric optimizes performance and HPC cluster deployment by eliminating the need for a discrete host fabric interface card.

Protecting the Future of Data

15-year product availability and 10-year use-case reliability helps protect your investment.

Other major enhancements:

  • Memory Technology: memory bandwith increase by factor 1.5, 6xDDR4 channels, 2133, 2400, 2666 MT/s, RDIMM, LRDIMM, Apache Pass
  • New CPU socket > Socket P
  • Scalable from 2 sockets – 4 sockets -8 sockets
  • Thermal Design Power (TDP) range from 70Watt up to 205Watt
  • New UltraPath Interconnect (UPI) 2-3 channel per processor up to 10.4 GigaTransfer per second
  • 48 PCIe lanes per processor with Bifurcation Support X16, X8, X4
    PCI Express uses serial communication and creates a drastically different scheme. Serial communication for PCI Express means setting up dedicated channels to each device in the system. Splitting the total amount of PCI Express channels into subgroups for specific PCI Express devices. This creation of PCI Express subgroups is PCI Express Bifurcation
  • PCH (Platform Controll Hub) Codename Lewisburg: DMI3  x4Chipset bus
  • Power Management: Per Core P-State (PCPS) – Uncore Frequency Scaling (UFS) – Energy Efficient Turbo (EET) – On die PMAX detection (NEW) – HW Controlled P-State (HWP) (NEW)
  • Rebalanced Cache Hierarchy: Increased MLC, 1.375 MB Last Level Cache/Core